This invention relates in general to semiconductor devices and masks, and more particularly, to semiconductor devices and masks having dummy features.
Polishing is used to planarize surfaces in forming semiconductor devices. Traditionally, no tiling has been used in forming semiconductor devices. When no tiling is used, polishing causes dishing or other problems related to nonuniform thickness across a semiconductor device substrate. These problems include exceeding the depth of focus for lithography or etch-related concerns that are illustrated in FIG. 1. FIG. 1 includes a substrate that includes a conductive layer 11. An insulating layer 12 is formed and patterned with openings extending to the conductive layer 11. A conductive fill material (e.g., tungsten or the like) is deposited into the openings and polished to form conductive plugs 13. The polishing can erode more of the insulating layer 12 where the conductive plugs are closely spaced. An insulating layer 16 is then formed over the conductive plugs 13. The upper surface of the insulating layer 16 is planar.
Openings 17 are then formed. In some locations, openings do not extend completely to all the conductive plugs 13 because of the erosion, thereby leaving an insulating gap 19 between an opening 17 and its underlying conductive plug 13 as shown in FIG. 1. An electrical open would be formed. If the etch is continued to remove gap 19, the conductive plugs 13 that are exposed earlier are overetched, typically resulting in high contact resistance. Therefore, the nonuniformity in thickness, caused in part by polishing, can result in electrical opens, high resistance contacts, electrical shorts, or other leakage paths.
Dummy features have been used as an attempt to solve the problems related to dishing and other accumulated thickness effects. Dummy features used to aid polishing are formed by xe2x80x9ctilingxe2x80x9d because, from a top view of the semiconductor device, the pattern of dummy features looks like tiles. The process for tiling typically includes creating a circuit layout, defining a buffer zone (typically in a range of approximately 5-10 microns) around active features within the layout, and combining the circuit layout with the minimum zone to determine excluded areas. All other areas are available for tiling.
Regardless of circuit density, tiling is used if the distance between any of active features is at or above a minimum width. Typically, the minimum width is no more than ten microns, and can be approximately ten microns. Tiles or at least partial tiles are placed in available areas at least five microns wide. The tiling pattern (i.e., size and density of tiles) is usually the same across a semiconductor device. See FIG. 5 in each of U.S. Pat. No. 5,278,105 and European Published Patent Application Number 0 712 156 (1996). Although portions of tiles are missing, the same feature density is used.